The present invention relates to a technique for reproducing compressed image data which may be recorded on optical discs, magnetic discs or the like and, more particularly, to such technique wherein the image data is compressed by a moving or motion picture experts group (MPEG) system.
A MPEG system may be utilized to compression-encode digital image signals which may be recorded in a digital video disc (hereinafter, a DVD). In the MPEG system, compression may be performed by utilizing predictive encoding and discrete cosine transform (DCT).
FIG. 8A illustrates a structure for interframe prediction in accordance with predictive encoding in an MPEG system. As shown therein, such structure or arrangement includes a plurality of frames or pictures. Each of such pictures is either an intraframe predictively encoded (I) picture, an interframe predictively encoded (P) picture or a bi-directionally predictively encoded (B) picture. A plurality of frames or pictures in a sequence of motion pictures may form a so-called group of pictures (GOP). For example, the GOP 1 of FIG. 8A has 15 frames which include one I picture or frame, four P pictures or frames, and ten B pictures or frames. A GOP may be utilized as an encoding unit.
An I picture may be formed or generated by using only image data of that one respective frame or picture and, as such, is an intraframe predictively encoded picture. A P picture may be formed from image data representing a temporally preceding and previously decoded I or P picture and, as such, is an interframe predictively encoded picture. In other words, a P picture is an interframe predictive encoded picture in a forward direction formed with reference to an already encoded and preceding (in time) I or P picture or frame. A B picture may be formed by using image data representing two frames--one preceding and another succeeding in time so as to be bi-directionally predictive encoded.
The above-described formation of the I, P and B pictures is illustrated in FIG. 8A. That is, the arrows illustrated in FIG. 8A indicate the picture or pictures utilized to form a respective picture. For example, the P picture P.sub.0 is predictively encoded with reference to I picture I.sub.0, P picture P.sub.1 is predictively encoded with reference to P picture P.sub.0, P picture P.sub.2 is predictively encoded with reference to P picture P1 and so forth. As another example, B pictures B.sub.0 and B.sub.1 are each predictively encoded with reference to both I picture I.sub.0 and P picture P.sub.0, B pictures B.sub.2 and B.sub.3 are each predictively encoded with reference to P pictures P.sub.0 and P.sub.1, and so forth. Since I picture I.sub.0 is predictively encoded by using only image data of that respective frame or picture, there are no arrows which indicate that picture I0 is formed with reference to another picture or pictures. As is to be appreciated, other I, P and B pictures are similarly formed.
Since an I picture may be predictively encoded by use of data within only the I picture or frame itself, such I picture may be decoded by use of only the I picture. On the other hand, since a respective P picture is predictively encoded with reference to the preceding I picture or P picture in time, such preceding I or P picture is required for the respective P picture to be decoded. In a similar manner, since a B picture is predictively encoded with reference to the preceding and succeeding I or P picture in time, such preceding or succeeding I or P picture is required for the B picture to be decoded. As a result, pictures may be rearranged such that the picture(s) required for decoding a respective picture are decoded prior to decoding the respective picture. For example, the pictures may be rearranged as shown in FIG. 8B. That is, since B pictures B.sub.-1 and B.sub.-2 require I picture I.sub.0 upon decoding, I picture I.sub.0 is arranged to precede B pictures B.sub.-1 and B.sub.-2. Since B pictures B.sub.0 and B.sub.1 require I picture I.sub.0 and P picture P.sub.0 upon decoding, P picture P.sub.0 is arranged to precede B pictures B.sub.0 and B.sub.1. (As is to be appreciated, I picture I0 already precedes B pictures B.sub.0 and B.sub.1.) Since B pictures B.sub.2 and B.sub.3 require P pictures P.sub.0 and P.sub.1 upon decoding, P picture P.sub.1 is arranged to precede B pictures B.sub.2 and B3. (As is to be appreciated, P picture P.sub.0 already precedes B pictures B2 and B.sub.3.) Since B pictures B.sub.4 and B.sub.5 require P pictures P.sub.1 and P.sub.2, P picture P.sub.2 is arranged to precede B pictures B.sub.4 and B.sub.5. (As is to be appreciated, P picture P.sub.1 already precedes B pictures B4 and B.sub.5.) For similar reasons, P picture P.sub.3 is arranged to precede B pictures B.sub.6 and B.sub.7.
The I, P and B pictures arranged as shown in FIG. 8B may be recorded in a DVD or other recording medium. Since the pictures are encoded by a MPEG system or in accordance with a MPEG standard as previously described, the quantity or amount of codes associated with each of the pictures may not be identical, but instead may be different depending on the complexity and the flatness of the respective images.
Pictures recorded in a DVD may be arranged within sectors in which each sector enables a predetermined quantity or amount of codes or data to be stored therein. As a result, one picture may occupy one, less than one or more than one sector. Furthermore, each picture is successively recorded in the sectors in a wrap-around manner. An example of a plurality of pictures recorded within sectors is illustrated in FIG. 9. As shown therein, I picture I.sub.0 is recorded in sector m, sector (m+1) and a portion of sector (m+2); B picture B.sub.-2 is recorded in the remaining region of sector (m+2) and sector (m+3); and so forth. In this example, 1 GOP is recorded from sector m to sector (m+21). However, the quantity of codes or data may be different for each GOP depending on the complexity or flatness of the images represented therein. Accordingly, the number of sectors required for recording the data of one GOP may be different between GOPs.
An apparatus for reproducing data which has been compressed and recorded by a MPEG system from a DVD is illustrated in FIG. 7. As shown therein, such apparatus generally includes a pickup 2, a demodulation circuit 3, a sector detection circuit 4, a ring buffer 5, a control circuit 6, a track jump judging circuit 7, a servo circuit 8, a phase locked loop (PLL) 9, an error correction circuit (ECC) 20 and a decoder 30. Such decoder 30 may include a video code buffer 10, an inverse variable length coding (VLC) circuit 11, an inverse quantization circuit 12, an inverse discrete cosine transform (DCT) circuit 13, an addition circuit 14, a motion compensation circuit 15, and a frame memory 16 which are coupled as shown in FIG. 7.
Digital data compressed by a MPEG system is recorded in tracks or sectors having a fixed length (as in FIG. 9) on a disc 1. A sector sync and a sector header may be added to a predetermined portion of each of the sectors, such as the top thereof. The disc 1 may be rotated in a predetermined rate or manner by a spindle motor (not shown). The pickup 2 produces a laser beam which is irradiated on the tracks of the optical disc 1 so as to read out the recorded data. Control for the pickup 2, such as focus control and tracking control, may be performed by the tracking and focus servo circuit 8. That is, the circuit 8 may provide a focused error signal and/or a tracking error signal to the pickup 2. Such focused and tracking error signals may be obtained from information read out from the pickup 2.
The read out digital data from the pickup 2 are supplied to the demodulation circuit 3, whereupon a predetermined demodulation such as EFM-demodulation is performed. (EFM is eight-to-fourteen modulation wherein a symbol having eight bits is converted to a symbol having fourteen bits.) The demodulated data is supplied to the sector detection circuit 4. The read out data from the pickup 2 are further supplied to the PLL circuit 9 so as form or regenerate clock signals which are supplied to the demodulation circuit 3 and the sector detection circuit 4. Such clock signals may be utilized in controlling the timing of the processing performed by the circuits 3 and 4.
As previously described, the sector detection circuit 4 receives demodulated data from the demodulation circuit 3. From such received data, the sector detection circuit 4 detects the sector sync so as to determine the boundary of the sectors and detects a sector address or the like from the sector header. An output signal representative of such detection(s) is supplied to the control circuit 6.
The demodulated data is supplied by way of the sector detection circuit 4 to the ECC circuit 20, whereupon error detection and correction may be performed. The error corrected data from the ECC circuit 20 is supplied to the ring buffer 5 and is written therein in accordance with a write control signal supplied by the control circuit 6.
The control circuit 6 generates the write control or write pointer (WP) signal based on the sector address for each of the sectors detected by the sector detection circuit 4 and supplies the WP signal to the ring buffer 5. Such WP signal indicates a write address wherein a sector may be written into the ring buffer 5. As a result of the WP signal, data from the ECC circuit 20 may be written into designated address locations of the ring buffer 5. The control circuit 6 further generates a read pointer (RP) signal based on a code request signal from the video code buffer 10 (in the succeeding stage of FIG. 7B) and supplies the RP signal to the ring buffer 5. Such RP signal indicates an address of data written into the ring buffer 5 which is desired to be read out. As a result, upon receiving a RP signal, data from the desired address location or position of the ring buffer 5 is read out and supplied to the video code buffer 10, whereupon such data is stored therein.
Therefore, the video code buffer 10 may generate a code request signal (which requests that data from the ring buffer 5 be transmitted to the video code buffer 10) and supply the same to the control circuit 6 whereupon, in response thereto, data is supplied from the ring buffer 5 to the video code buffer 10. The video code buffer 10 may further receive a code request signal from the inverse VLC circuit 11. In response thereto, data stored in the video code buffer 10 may be supplied to the inverse VLC circuit 11, whereupon inverse VLC processing is performed. Upon completing such inverse VLC processing, the processed data may be supplied to the inverse quantization circuit 12 and another code request signal may be supplied to the video code buffer 10 so as to request new data therefrom. The inverse VLC circuit 11 may also supply the size of a quantization step to the inverse quantization circuit 12 and a motion vector information signal to the motion compensation circuit 15.
The inverse quantization circuit 12 inversely quantizes the data received from the inverse VLC circuit 11 in accordance with the size of the quantization step and outputs the obtained processed signal to the inverse DCT circuit 13, whereupon inverse DCT processing is performed. An output signal from the inverse DCT circuit 13 is supplied to one input terminal of the addition circuit 14. An output from the motion compensation circuit 15 formed in accordance with the type of picture (that is, I, P or B), as hereinafter more fully described, is supplied to another input terminal of the addition circuit 14. The addition circuit 14 adds the received signals and supplies the obtained summed signal, by way of a switch 16d, through the appropriate one of contacts A-C to one of memories 16a, 16b and 16c of the frame memory bank 16 so as to be stored therein. Stored signals from the memories 16a, 16b and 16c may be supplied to the motion compensation circuit 15.
The operation performed by the motion compensation circuit 15 and the frame memory bank 16 will now be further described. For this discussion, assume that a recording frame shown in FIG. 8B is reproduced. If the respective reproduced frame is an I picture or frame, then interframe prediction is not applied to such I picture upon decoding. As a result, a zero or no output signal is supplied from the motion compensation circuit 15 to the addition circuit 14 so that the output signal from the inverse DCT circuit 13 is supplied to the frame memory bank 16. However, if the respective reproduced frame is a P picture or a B picture, then the decoded I or P picture(s) needed to decode such respective P or B picture (the decoded I or P picture corresponds to the picture or pictures utilized during predictive encoding) is supplied from the appropriate one of the memories 16a, 16b or 16c of the frame memory bank 16 to the motion compensation circuit 15, wherein a motion prediction image signal is formed with the motion vector information supplied from the inverse VLC circuit 11 and supplied to the addition circuit 14. As a result, the motion prediction image signal and the output signal from the inverse DCT circuit 13 are added in the addition circuit 14 so as to decode the respective picture and the decoded picture is stored in the frame memory bank 16.
Data from the memories 16a-16c of the frame memory 16 are read out under control through contacts A-C by way of a switch 16e so as to restore the original frame order, such as to that shown in FIG. 8A. The read out data are converted by a digital-to-analog (D/A) converter 17 into analog video signals and supplied to a display 18 so as to be displayed thereon.
Therefore, the control circuit 6 causes data stored in the ring buffer 5 to be supplied to the video code buffer 10 in accordance with the code request signal from the video code buffer 10. When data processing of relatively simple video images is being performed and the amount of data transmitted from the video code buffer 10 to the inverse VLC circuit 11 decreases, the amount of data transmitted from the ring buffer 5 to the video code buffer 10 may also decrease. As a result, the amount of data stored in the ring buffer 5 may increase so as to cause an overflow condition of the ring buffer 5. In other words, the amount of data written into the ring buffer 5 by use of the WP signal may surpass the amount read out therefrom by use of the RP signal. To avoid such overflow condition, the quantity of data currently stored in the ring buffer 5 may be determined or calculated by, for example, utilizing address positions of the WP and RP signals controlled by the control circuit 6. Such determination may be performed by the track jump judging circuit 7. If the amount of the data determined to be stored in the ring buffer 5 exceeds a predetermined reference value, a track jump instruction signal is generated by the track jump judging circuit 7 and supplied therefrom to the tracking servo circuit 8. As a result, the pickup 2 may move or jump from the current track to another track. Therefore, the track jump judging circuit 7 determines if the ring buffer 5 may overflow and outputs a track jump instruction signal in response to such determination so as to cause the pickup to jump.
The rate at which data is transmitted from the ring buffer 5 to the video code buffer 10 may be equal to or smaller than the rate at which data is transmitted from the ECC circuit 20 to the ring buffer 5. As is to be appreciated, such arrangement of transmission rates prevents the ring buffer 5 from being depleted of data. Furthermore, such arrangement of transmission rates enables the video code buffer 10 to transmit a code request signal to the ring buffer 5 irrespective of the timing of the track jump. As previously described, such code request signal requests that data from the ring buffer 5 be transmitted to the video code buffer 10.
Therefore, the data reproducing apparatus of FIG. 7 causes the pickup 2 to track jump in accordance with the memory capacity of the ring buffer 5. As a result, overflow or underflow of the video code buffer 10 may be prevented, irrespective of the complexity or flatness of the video images recorded in the disc 1, so as to enable video images of uniform image quality to be continuously reproduced.
Although the data reproducing apparatus of FIG. 7 may perform satisfactorily when operating in a normal reproduction mode, problems may arise when such apparatus performs so-called random accessing or operates in other modes such as a mode transition. More specifically, compression-encoded picture data having an order of . . . , B.sub.-4, B.sub.-3, P.sub.-1, B.sub.-2, B.sub.-1, I.sub.0, B.sub.0, B.sub.1, P.sub.0, . . . as shown in FIG. 10A may be rearranged as described above and as shown in FIG. 10B and recorded in the disc 1 (FIG. 7). In a normal reproduction or regeneration mode, if picture data read out from the disc 1 are decoded successively and stored in the memory bank 16, the stored decoded data can be read out from the frame memory bank 16 in the display order shown in FIG. 10A. However, when random accessing (such as, a track search, a chapter search or a time code search) or a mode transition is to be performed, an entry point is utilized. For example, such entry point may be defined at a position corresponding to I picture I.sub.0 as shown in FIG. 10C. In this example, picture data are read out from the disc 1 in the order of I.sub.0, B.sub.-2, B.sub.-1, P.sub.0, B.sub.0, B.sub.1, . . . , as shown in FIG. 10C. The I picture I.sub.0 is an intraframe predictively encoded image which can be decoded by utilizing only the I.sub.0 picture. However, the B pictures B.sub.-2 and B.sub.-1 require P picture P.sub.-1 and I picture I.sub.0 for decoding. Since processing begins at the entry point of the I picture I.sub.0, the P picture P-1 has not been read out and decoded. Accordingly, the B pictures B.sub.-2 and B.sub.-1 cannot be correctly decoded. As a result, incorrectly decoded B pictures B-2 and B-1 are supplied from the decoder 30 to the display 18 (FIG. 7B), thereby causing deformed images to be displayed thereon.